Automatic test equipment (ATE) often plays a crucial role in the fabrication of semiconductor devices. The equipment allows a manufacturer to functionally test its devices, ensuring device operability at pre-set specifications prior to entering the marketplace. Utilized as a measurement tool, the equipment typically provides electronic channels that correspond to the input and output pins of a semiconductor device. The device is typically inserted in a test socket that forms a portion of a device-interface-board (DIB). By sending signals to and retrieving signals from the device, operation in a real-world environment may be simulated by the ATE.
There are often instances where an ATE user wishes to isolate and select one channel from a group of tester channels. Calibrating the channel to a reference and validating the channel timing accuracy are but a few examples. A straightforward way to select one channel from a group of channels is to employ a multiplexer on the DIB.
Typical multiplexers include a plurality of input pins and a switching scheme for activating a selected pin. The switching circuitry terminates in a common node, which then completes a signal path to the multiplexer output pin. Input signals received on the pin are then passed through the multiplexer along the common node, and passed through to the multiplexer output. In this manner, a digital signal propagating along an activated channel is passed directly through the multiplexer, and on to the calibration or validation circuitry.
While this straightforward selection scheme works well for its intended low-frequency applications, the basic structure can be problematic for high-speed (frequency) applications. The problems are primarily caused by a relatively large capacitance on the common node, due to the numerous parallel connections to the switches associated with the input pins. Signals passed through a single channel to the node are susceptible to RC effects at the node (from charging and discharging the capacitance, etc.), often significantly affecting the quality of the rising and falling edges of the signal. This is an undesirable problem for high-accuracy ATE, where edge placement timing accuracy may be a critical parameter.
What is needed and currently unavailable is a high-speed digital multiplexer that avoids the parasitic problem described above. The high-speed digital multiplexer of the present invention satisfies this need.